library ieee;
use ieee.std_logic_1164.all;

entity sl2 is
    port ( a : in std_logic_vector(31 downto 0);
            y : out std_logic_vector(31 downto 0));
end entity;

architecture arch of sl2 is
begin
    process (a)
    begin
        for i in 31 downto 2 loop
           y(i) <= a(i - 2);
        end loop;
        
        y(0) <= '0';
        y(1) <= '0';
    end process;
end architecture;
